High temperature processing of silicon wafers is important for manufacturing modern microelectronics devices. Such processes, including silicide formation, implant anneals, oxidation, diffusion drive-in and chemical vapor deposition (CVD), may be performed at high temperatures using conventional thermal processing techniques. Furthermore, many microelectronics circuits require feature sizes smaller than one micron and junction depths less than a few hundred angstroms. In order to limit both the lateral and downward diffusion of dopants, as well as to provide a greater degree of control during processing, it is desirable to minimize the duration of high temperature processing.
Semiconductor wafers, flat panel displays and other similar substrates typically have numerous material layers deposited thereon during device fabrication. Some commonly deposited layers (e.g., spin-on glass (SOG) films) may contain contaminants, defects or undesirable microstructures that can be reduced in number or altogether removed by heating or “annealing” the substrate at an appropriate temperature for an appropriate time. Other deposited layers (e.g., copper films) may have properties that undesirably change over time or “self-anneal”, resulting in unpredictable deposited layer properties (e.g., unpredictable resistivity, stress, grain size, hardness, etc.). As with contaminants, defects, and undesirable microstructures, deposited layer properties often can be stabilized by a controlled annealing step. Following the annealing step, the substrate preferably is rapidly cooled to stop the annealing process, and so that other processes can be performed on the substrate, in order to increase throughput.
Conventionally, annealing is performed within a quartz furnace that must be slowly pre-heated to a desired annealing temperature, or within a rapid thermal process (RTP) system that can be rapidly heated to a desired annealing temperature. Thereafter, an annealed substrate is transferred to a separate cooling module that conventionally employs a cooled substrate support and is slightly backfilled with a gas such as helium to enhance thermal conduction. The separate cooling module increases equipment cost and complexity, as well as equipment footprint, and decreases substrate throughput by requiring undesirable substrate transfer time between the heating and cooling systems.
Another approach for minimizing processing time utilizes a heat treatment apparatus such as a single-wafer RTP system. Single-wafer rapid thermal processing of semiconductor wafers provides a powerful and versatile technique for fabrication of very-large-scale-integrated (VLSI) and ultra-large-scale-integrated (ULSI) electronic devices. There are several challenges, however, to meeting the thermal requirements of rapid thermal processing. For example, fast rates of change of wafer temperature are typically desired, as well as temperature uniformity across the wafer during the temperature changes.
According to one single-wafer lamp-based RTP system of the prior art, for example, the wafer is vertically translated between a position proximate to a heating lamp and a position proximate to a solid cold plate. When the wafer is translated from the position proximate to the heating lamp to the position proximate to the cold plate, rapid temperature changes occur during what is termed “ramp-down”, wherein the temperature of the wafer desirably decreases rapidly to a predetermined temperature. The temperature variation across the wafer during ramp-down, however, should be sufficiently uniform during cooling in order to prevent damage to the wafer such as warpage or cracking. Accordingly, a temperature profile of the cold plate should be substantially uniform across the surface thereof.
According to the exemplary prior art lamp-based RTP system, several translating pins are utilized in order to translate the wafer between the cold plate and the heating lamp, wherein the pins vertically translate through holes in the cold plate, thereby supporting the wafer. In a lamp-based RTP system, however, a distance which the wafer travels between the heat lamp and the cold plate is minimal, since thermal radiation transmitted by the heat lamp can be substantially limited by, for example, cutting power to the heat lamp, or by shielding the wafer by a shutter. Therefore, since the distance of travel between the heating lamp and the cold plate is relatively short, the pins are typically relatively short in length. Consequently, the pins may have significantly small diameters, whereby linear integrity over the short length of the pins can be achieved with the relatively small diameters. Having small diameter pins further minimizes a dimension of the holes in the cold plate, through which the pins translate. Limiting the dimension of the holes in the cold plate is of great concern, since the size of the holes in the cold plate plays a significant role in thermal uniformity across the cold plate during ramp-down. Accordingly, larger holes that may accommodate larger diameter pins may have detrimental effects on the thermal uniformity across the cold plate, and hence, can lead to detrimental effects on the temperature uniformity of the wafer during cooling.
As illustrated in FIG. 1, a simplified lamp-based RTP system 10 of the prior art is depicted, wherein the system comprises a heater lamp 20, a wafer holder assembly 30 and a single-piece cold plate 40. The wafer holder assembly 30 further comprises pins 50 that support the wafer 60, wherein the pins are operable to translate through holes 70 in the cold plate 40 to permit the wafer 60 to be translated between the heater lamp 20 and the cold plate. Typically, a distance between the heater lamp 20 and the cold plate 40 is small (e.g., less than an 20 mm), as discussed above, wherein the diameter of the pins 50 and the holes 70 are respectively small.
The system 10 of the prior art, however may suffer detrimental effects if the distance between the heater lamp 20 and the cold plate 40 is significantly increased. Vertical furnaces, for example, typically translate a wafer over a large distance (e.g., 300 mm or more) within a heater chamber, thereby typically requiring a more robust wafer holder assembly. Furthermore, the substantially solid cold plate 40 utilized in the prior art cannot typically be utilized in a vertical furnace where backside temperature sensing during heating of the wafer is performed. Since a significantly large-diameter hollow elevator shaft (e.g., 10 mm diameter) and accompanying temperature sensing equipment is typically utilized in a vertical furnace RTP chamber, a significantly large hole in the sole cold plate would be needed to accommodate the elevator. Such a large hole would adversely affect the thermal uniformity across the cold plate, and thus, the temperature uniformity across the wafer during cooling.
The conventional cold plate 40 of the prior art may further comprise a plurality of gas ports (not shown) in the cold plate 40 to generally provide a cooling gas to the wafer 60, whereby cooling of the wafer in the molecular flow regime can occur. Cooling in the molecular regime is generally caused by a flowing of gas molecules over a distance which is less than the mean free path for these molecules. However, cooling of the wafer 60 in the molecular flow regime generally limits an ability to fine-tune a temperature profile across the wafer 60.
Therefore, for at least the above-mentioned reasons, an improved cold plate for a vertical furnace RTP system and a method for cooling a wafer is needed to alleviate many of the problems associated with the prior art.